?002 fairchild semiconductor corporation january 2002 rev .b, january 2002 IRFP250N IRFP250N n-channel power mosfet 200v, 30a, 0.075 ? features ultra low on-resistance -r ds(on) = 0.052 ? (typ) , v gs = 10v simulation models - temperature compensated pspice?and saber electrical models - spice and saber thermal impedance models peak current vs pulse width curve uis rating curve mosfet maximum ratings t a = 25? unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v dss drain to source voltage 200 v v gs gate to source voltage 20 v i d drain current 30 a continuous (t c = 25 o c, v gs = 10v) continuous (t c = 100 o c, v gs = 10v) 21 a pulsed figure 4 a e as single pulse avalanche energy (note 1) 315 mj p d power dissipation derate above 25 o c 214 1.4 w w/ o c t j , t stg operating and storage temperature -55 to 175 o c r jc thermal resistance junction to case to-247 0.70 o c/w r ja thermal resistance junction to ambient to-247 40 o c/w device marking device package reel size tape width quantity IRFP250N IRFP250N to-247 tube n/a 30 d g s source drain gate drain (tab) to-247
?002 fairchild semiconductor corporation rev. b, january 2002 IRFP250N electrical characteristics t a = 25? unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics (v gs = 10v) drain-source diode characteristics notes: 1: starting t j = 25?, l = 1.9mh, i as = 18a. 2: pulse width 300 s; duty cycle 2%. symbol parameter test conditions min typ max units b vdss drain to source breakdown voltage i d = 250 a, v gs = 0v 200 - - v i dss zero gate voltage drain current v ds = 200v v gs = 0v - - 25 a v ds = 160v t c = 150 o - - 250 i gss gate to source leakage current v gs = 20v - - 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a2-4v r ds(on) drain to source on resistance i d = 18a, v gs = 10v - 0.052 0.075 ? g fs forward transconductance v ds = 50v, i d = 18a (note 2) 17 - - s c iss input capacitance v ds = 25v, v gs = 0v, f = 1mhz - 4023 - pf c oss output capacitance - 880 - pf c rss reverse transfer capacitance - 240 - pf q g(tot) total gate charge at 20v v gs = 0v to 20v v dd = 160v i d = 18a i g = 2.0ma 215 280 nc q g(10) total gate charge at 10v v gs = 0v to 10v - 114 140 nc q g(th) threshold gate charge v gs = 0v to 2v - 8 10 nc q gs gate to source gate charge - 14 - nc q gd gate to drain ?iller charge - 44 - nc t on turn-on time v dd = 100v, i d = 18a v gs = 10v, r gs = 3.9 ? - - 69 ns t d(on) turn-on delay time - 16 - ns t r rise time - 30 - ns t d(off) turn-off delay time - 78 - ns t f fall time - 40 - ns t off turn-off time - - 177 ns v sd source to drain diode voltage i sd = 18a - - 1.3 v t rr reverse recovery time i sd = 18a, di sd /dt = 100a/ s - - 279 ns q rr reverse recovered charge i sd = 18a, di sd /dt = 100a/ s - - 2000 nc
?002 fairchild semiconductor corporation rev. b, january 2002 IRFP250N typical characteristic figure 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capability t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 175 0.2 0.4 0.6 0.8 1.0 1.2 125 150 0 10 20 30 40 25 50 75 100 125 150 175 i d , drain current (a) t c , case temperature ( o c) v gs = 10v 0.1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 2 t, rectangular pulse duration (s) z jc , normalized thermal impedance notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 0.5 0.2 0.1 0.05 0.01 0.02 duty cycle - descending order single pulse 10 100 1000 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -5 i dm , peak current (a) t, pulse width (s) transconductance may limit current in this region t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: v gs = 10v
?002 fairchild semiconductor corporation rev. b, january 2002 IRFP250N figure 5. forward bias safe operating area figure 6. unclamped inductive switching capability figure 7. transfer characteristics figure 8. saturation characteristics figure 9. normalized drain to source on resistance vs junction temperature figure 10. normalized gate threshold voltage vs junction temperature typical characteristic (continued) 1 10 100 1 10 100 500 500 v ds , drain to source voltage (v) i d , drain current (a) t j = max rated t c = 25 o c single pulse 100 s 10ms 1ms limited by r ds(on) area may be operation in this 1 10 100 0.001 0.01 0.1 1 200 10 i as , avalanche current (a) t av , time in avalanche (ms) starting t j = 25 o c starting t j = 150 o c t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] 0 25 50 75 234 5 i d, drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j = 175 o c t j = 25 o c t j = -55 o c 0 25 50 75 0123456 i d , drain current (a) v ds , drain to source voltage (v) v gs =4.5v pulse duration = 80 s duty cycle = 0.5% max t c = 25 o c v gs = 10v v gs = 5v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -80 -40 0 40 80 120 200 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d = 30a pulse duration = 80 s duty cycle = 0.5% max 160 0.4 0.6 0.8 1.0 1.2 -80 -40 0 40 80 120 160 200 normalized gate t j , junction temperature ( o c) v gs = v ds , i d = 250 a threshold voltage
?002 fairchild semiconductor corporation rev. b, january 2002 IRFP250N figure 11. normalized drain to source breakdown voltage vs junction temperature figure 12. capacitance vs drain to source voltage figure 13. gate charge waveforms for constant gate currents typical characteristic (continued) 0.9 1.0 1.1 1.2 1.3 -80 -40 0 40 80 120 160 200 t j , junction temperature ( o c) normalized drain to source breakdown voltage i d = 250 a 100 1000 10000 0.1 1.0 10 100 200 30 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss ? c ds + c gd 0 2 4 6 8 10 0 20406080100120 v gs , gate to source voltage (v) v dd = 160v q g , gate charge (nc) i d = 18a i d = 10a waveforms in descending order: test circuits and waveforms figure 14. unclamped energy test circuit figure 15. unclamped energy waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0
?002 fairchild semiconductor corporation rev. b, january 2002 IRFP250N figure 16. gate charge test circuit figure 17. gate charge waveforms figure 18. switching time test circuit figure 19. switching time waveforms test circuits and waveforms (continued) r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 2v q g(10) v gs = 10v q g(tot) v gs = 20v v ds v gs i g(ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0
?002 fairchild semiconductor corporation rev. b, january 2002 IRFP250N pspice electrical model .subckt IRFP250N 2 1 3 ; rev may 2001 ca 12 8 6.6e-9 cb 15 14 6.5e-9 cin 6 8 3.80e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 221 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1.0e-9 lgate 1 9 8.05e-9 lsource 3 7 5.8e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 5.0e-2 rgate 9 20 0.77 rldrain 2 5 10 rlgate 1 9 80.5 rlsource 3 7 58 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 1.8e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*100),2.5))} .model dbodymod d (is = 2.8e-12 rs = 3.0e-3 xti = 5.5 trs1 = 3.5e-3 trs2 = 1e-5 cjo = 2.55e-9 tt = 1.52e-7 m = 0.42) .model dbreakmod d (rs = 1.2e-0 trs1 = 1e-3 trs2 = 1e-6) .model dplcapmod d (cjo = 4.6e-9 is = 1e-30 n = 10 m = 0.9) .model mmedmod nmos (vto = 3.05 kp = 2.5 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 0.77) .model mstromod nmos (vto = 3.55 kp = 100 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 2.69 kp = 0.05 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 7.70 ) .model rbreakmod res (tc1 =1.27e-3 tc2 = 1.0e-6) .model rdrainmod res (tc1 = 9.90e-3 tc2 = 3.60e-5) .model rslcmod res (tc1 = 3.0e-3 tc2 = 1.0e-6) .model rsourcemod res (tc1 = 1e-3 tc2 = 1e-6) .model rvthresmod res (tc1 = -2.90e-3 tc2 = -1.10e-5) .model rvtempmod res (tc1 = -2.80e-3 tc2 = 1.70e-7) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -5.5 voff= -4.5) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -4.5 voff= -5.5) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -0.3 voff= 0.4) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.4 voff= -0.3) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6
?002 fairchild semiconductor corporation rev. b, january 2002 IRFP250N saber electrical model rev may 2001 template IRFP250N n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 2.8e-12, rs = 3.0e-3, xti = 5.5, trs1 = 3.5e-3, trs2 = 1.0e-5, cjo = 2.55e-9, tt = 1.52e-7, m = 0. 42) dp..model dbreakmod = (rs = 1.2, trs1 = 1.0e-3, trs2 = 1.0e-6) dp..model dplcapmod = (cjo = 4.6e-9, isl = 10e-30, nl=10, m = 0.9) m..model mmedmod = (type=_n, vto = 3.05, kp = 2.5, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.55, kp = 100, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.69, kp = 0.05, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -4.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -4.5, voff = -5.5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.4) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.4, voff = -0.3) c.ca n12 n8 = 6.6e-9 c.cb n15 n14 = 6.5e-9 c.cin n6 n8 = 3.8e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.00e-9 l.lgate n1 n9 = 8.05e-9 l.lsource n3 n7 = 5.80e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.27e-3, tc2 = 1.00e-6 res.rdrain n50 n16 = 5.0e-2, tc1 = 9.9e-3, tc2 =3.6e-5 res.rgate n9 n20 = 0.77 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 80.5 res.rlsource n3 n7 = 58 res.rslc1 n5 n51= 1e-6, tc1 = 3e-3, tc2 = -1.0e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.8e-3, tc1 = 1.0e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.8e-3, tc2 = 1.70e-6 res.rvthres n22 n8 = 1, tc1 = -2.9e-3, tc2 = 1.1e-5 spe.ebreak n11 n7 n17 n18 = 221 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6*100))** 2.5)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6
?002 fairchild semiconductor corporation rev. b, january 2002 IRFP250N spice thermal model rev may 2001 IRFP250N ctherm1 th 6 6.45e-3 ctherm2 6 5 3.00e-2 ctherm3 5 4 1.40e-2 ctherm4 4 3 1.65e-2 ctherm5 3 2 4.85e-2 ctherm6 2 tl 1.00e-1 rtherm1 th 6 3.24e-3 rtherm2 6 5 8.08e-3 rtherm3 5 4 2.28e-2 rtherm4 4 3 1.00e-1 rtherm5 3 2 1.10e-1 rtherm6 2 tl 1.40e-1 saber thermal model saber thermal model IRFP250N template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 6.45e-3 ctherm.ctherm2 6 5 = 3.00e-2 ctherm.ctherm3 5 4 = 1.40e-2 ctherm.ctherm4 4 3 = 1.65e-2 ctherm.ctherm5 3 2 = 4.85e-2 ctherm.ctherm6 2 tl = 1.00e-1 rtherm.rtherm1 th 6 = 3.24e-3 rtherm.rtherm2 6 5 = 8.08e-3 rtherm.rtherm3 5 4 = 2.28e-2 rtherm.rtherm4 4 3 = 1.00e-1 rtherm.rtherm5 3 2 = 1.10e-1 rtherm.rtherm6 2 tl = 1.40e-1 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
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